The present invention relates generally to memory circuits and, more particularly, to a memory circuit utilizing a voltage differential sensing circuit that senses a data signal during a data output operation. More particularly still, the present invention relates to a voltage differential sensing circuit that reduces timing delay by holding a midpoint value before switching from a first state to a second state when outputting a data signal from the memory array.
A conventional output buffer circuit transmits binary data signals of high and low potentials from an input node to an output node. The high and low potentials represent two states of the output buffer circuit.
These states constitute the unit of information typically stored and retrieved in digital systems, also known as a data bit. A data bit is a binary number having a value of 0 or 1. A data bit in a digital system has logic states of xe2x80x9chighxe2x80x9d and xe2x80x9clow,xe2x80x9d often corresponding to a physical parameter such as the voltage at a node in a circuit. Information stored in semiconductor circuits is quantified in terms of the number of bits stored. These circuits, collectively called memory devices, include latches, flip-flops, and registers, depending to some extent on the number of bits stored. The memory cell is the fundamental circuit, however, for storing a data bit and is the building block from which latches, flip-flops, registers, and the like are made.
Several common circuits have been used for the memory cell in the various types of memory devices. Some devices, including the dynamic random access memory (DRAM), employ a memory cell circuit typically having one transistor. The DRAM cell provides one signal for storage data. Other devices, including the static random access memory (SRAM), employ a memory cell circuit having primarily a cross-coupled pair of transistors. The SRAM cell provides two complementary signals for storing data. For example, with complementary signals D and D*, a 0 is represented when D is low and D* is high; and a 1 is represented when D is high and D* is low. Other combinations of D and D* are undefined and thus serve no purpose in the memory device.
Memory devices that are used for storing many bits of information provide an output data signal in response to an input address signal during a xe2x80x9creadxe2x80x9d operation called a read cycle. In a complex memory device, the read operation may be performed as a process of selecting, sensing, and outputting the content of memory cells. The duration of such a process is called the access time. Complex memory devices may have several types of operations distinguished by control signals including read/write, address strobes, programming and errata strobes, transfer enable and output enable signals. The read cycle begins when the operation is defined by these control signals and an address is specified on the address input of the memory device.
The address can be specified in one of several ways, depending on the design of the memory device. For example, an address can be specified in serial, in conjunction with a clock signal, or in parallel, often accompanied by a strobe signal. A combination of these methods could be used, for example, by presenting on 16 parallel address lines a 32-bit address in two steps accompanied by upper and lower address strobes. In a conventional DRAM, these strobes are associated with the row and column organization of memory cells in an array. Designs for high density memory devices employ several arrays of cells having minute dimensions. Typically, the signal or signals representing the data bit in a memory cell in such an array are weak.
The read cycle concludes with the presentation of signals for use outside the memory device that represent the data addressed. The weak signal levels internal to the memory device are sensed and amplified. Amplified signals at internal signal levels are then translated to conventional logic levels and gated onto the output terminals of the memory device. The level translation and gating are accomplished by an output buffer circuit. When the output buffer circuit is supplying a signal on the output terminal, it is said to be gated on, or enabled; otherwise, it is off or disabled. One aspect important in the design of memory arrays is developing faster timing transitions between the inner action of the sensing circuit and the output buffer circuit.
One example where timing is an issue is in the use of voltage differential sensing circuits within a memory array. Typically, a voltage differential sensing circuit (hereinafter sensing circuit) is used to amplify an output signal from a memory array, but a transition from one potential to the other has to ripple through the sensing circuit as quickly as possible. Typically, the helper flip-flop must transition from a first potential to a second potential and a delay occurs because of such a transition in the worst case example.
Accordingly, what is needed is a method and apparatus that reduces the transition delay from one potential to another within a sensing circuit when outputting a sensed signal in a memory device.
According to the present invention, a sensing circuit is disclosed for use in a memory device. The sensing circuit utilizes the inherent delay between when the enable signal is enabled and when data is valid by pulling the output gate of the sensing circuit to a midpoint voltage. As the output starts at a midpoint voltage, the voltage swing to valid data is faster because the output no longer needs to swing from a maximum voltage level to a minimum voltage level as before.